AMD
by AMD
CVEs (8)
| CVE | Vendor / Product | Sev | Risk | CVSS | EPSS | KEV | Published | Description |
|---|---|---|---|---|---|---|---|---|
| CVE-2023-31345 | Hig | 0.49 | 7.5 | 0.00 | Feb 12, 2025 | Improper input validation in the SMM handler may allow a privileged attacker to overwrite SMRAM, potentially leading to arbitrary code execution. | ||
| CVE-2023-31343 | Hig | 0.49 | 7.5 | 0.00 | Feb 11, 2025 | Improper input validation in the SMM handler may allow a privileged attacker to overwrite SMRAM, potentially leading to arbitrary code execution. | ||
| CVE-2023-31342 | Hig | 0.49 | 7.5 | 0.00 | Feb 11, 2025 | Improper input validation in the SMM handler may allow a privileged attacker to overwrite SMRAM, potentially leading to arbitrary code execution. | ||
| CVE-2023-31315 | Hig | 0.49 | 7.5 | 0.01 | Aug 12, 2024 | Improper validation in a model specific register (MSR) could allow a malicious program with ring0 access to modify SMM configuration while SMI lock is enabled, potentially leading to arbitrary code execution. | ||
| CVE-2021-28695 | Med | 0.44 | 6.8 | 0.00 | Aug 27, 2021 | IOMMU page mapping issues on x86 T[his CNA information record relates to multiple CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Both AMD and Intel allow ACPI tables to specify regions of memory which should be left untranslated, which typically… | ||
| CVE-2024-36315 | Med | 0.37 | — | 0.00 | May 13, 2026 | Improper enforcement of the LFENCE serialization property may allow an attacker to bypass speculation barriers and potentially disclose sensitive information, potentially resulting in loss of confidentiality. | ||
| CVE-2024-36350 | Med | 0.36 | 5.6 | 0.00 | Jul 8, 2025 | A transient execution vulnerability in some AMD processors may allow an attacker to infer data from previous stores, potentially resulting in the leakage of privileged information. | ||
| CVE-2021-26407 | Med | 0.36 | 5.5 | 0.00 | Jan 11, 2023 | A randomly generated Initialization Vector (IV) may lead to a collision of IVs with the same key potentially resulting in information disclosure. |
- risk 0.49cvss 7.5epss 0.00
Improper input validation in the SMM handler may allow a privileged attacker to overwrite SMRAM, potentially leading to arbitrary code execution.
- risk 0.49cvss 7.5epss 0.00
Improper input validation in the SMM handler may allow a privileged attacker to overwrite SMRAM, potentially leading to arbitrary code execution.
- risk 0.49cvss 7.5epss 0.00
Improper input validation in the SMM handler may allow a privileged attacker to overwrite SMRAM, potentially leading to arbitrary code execution.
- risk 0.49cvss 7.5epss 0.01
Improper validation in a model specific register (MSR) could allow a malicious program with ring0 access to modify SMM configuration while SMI lock is enabled, potentially leading to arbitrary code execution.
- risk 0.44cvss 6.8epss 0.00
IOMMU page mapping issues on x86 T[his CNA information record relates to multiple CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Both AMD and Intel allow ACPI tables to specify regions of memory which should be left untranslated, which typically…
- risk 0.37cvss —epss 0.00
Improper enforcement of the LFENCE serialization property may allow an attacker to bypass speculation barriers and potentially disclose sensitive information, potentially resulting in loss of confidentiality.
- risk 0.36cvss 5.6epss 0.00
A transient execution vulnerability in some AMD processors may allow an attacker to infer data from previous stores, potentially resulting in the leakage of privileged information.
- risk 0.36cvss 5.5epss 0.00
A randomly generated Initialization Vector (IV) may lead to a collision of IVs with the same key potentially resulting in information disclosure.