microprocessor
by Intel
CVEs (8)
| CVE | Vendor / Product | Sev | Risk | CVSS | EPSS | KEV | Published | Description |
|---|---|---|---|---|---|---|---|---|
| CVE-2018-12130 | Med | 0.38 | 5.9 | 0.02 | May 30, 2019 | Microarchitectural Fill Buffer Data Sampling (MFBDS): Fill buffers on some microprocessors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access. A list of impacted products can be found… | ||
| CVE-2022-29901 | Med | 0.37 | 5.6 | 0.05 | Jul 12, 2022 | Intel microprocessor generations 6 to 8 are affected by a new Spectre variant that is able to bypass their retpoline mitigation in the kernel to leak arbitrary data. An attacker with unprivileged user access can hijack return instructions to achieve arbitrary speculative code… | ||
| CVE-2018-12127 | Med | 0.37 | 5.6 | 0.01 | May 30, 2019 | Microarchitectural Load Port Data Sampling (MLPDS): Load ports on some microprocessors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access. A list of impacted products can be found… | ||
| CVE-2018-12126 | Med | 0.37 | 5.6 | 0.01 | May 30, 2019 | Microarchitectural Store Buffer Data Sampling (MSBDS): Store buffers on some microprocessors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access. A list of impacted products can be… | ||
| CVE-2019-11091 | Med | 0.36 | 5.6 | 0.01 | May 30, 2019 | Microarchitectural Data Sampling Uncacheable Memory (MDSUM): Uncacheable memory on some microprocessors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access. A list of impacted products… | ||
| CVE-2019-11184 | Med | 0.31 | 4.8 | 0.01 | Sep 16, 2019 | A race condition in specific microprocessors using Intel (R) DDIO cache allocation and RDMA may allow an authenticated user to potentially enable partial information disclosure via adjacent access. | ||
| CVE-2019-0162 | Low | 0.25 | 3.8 | 0.01 | Apr 17, 2019 | Memory access in virtual memory mapping for some microprocessors may allow an authenticated user to potentially enable information disclosure via local access. | ||
| CVE-2019-0174 | Low | 0.21 | 3.3 | 0.00 | Jun 13, 2019 | Logic condition in specific microprocessors may allow an authenticated user to potentially enable partial physical address information disclosure via local access. |
- risk 0.38cvss 5.9epss 0.02
Microarchitectural Fill Buffer Data Sampling (MFBDS): Fill buffers on some microprocessors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access. A list of impacted products can be found…
- risk 0.37cvss 5.6epss 0.05
Intel microprocessor generations 6 to 8 are affected by a new Spectre variant that is able to bypass their retpoline mitigation in the kernel to leak arbitrary data. An attacker with unprivileged user access can hijack return instructions to achieve arbitrary speculative code…
- risk 0.37cvss 5.6epss 0.01
Microarchitectural Load Port Data Sampling (MLPDS): Load ports on some microprocessors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access. A list of impacted products can be found…
- risk 0.37cvss 5.6epss 0.01
Microarchitectural Store Buffer Data Sampling (MSBDS): Store buffers on some microprocessors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access. A list of impacted products can be…
- risk 0.36cvss 5.6epss 0.01
Microarchitectural Data Sampling Uncacheable Memory (MDSUM): Uncacheable memory on some microprocessors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access. A list of impacted products…
- risk 0.31cvss 4.8epss 0.01
A race condition in specific microprocessors using Intel (R) DDIO cache allocation and RDMA may allow an authenticated user to potentially enable partial information disclosure via adjacent access.
- risk 0.25cvss 3.8epss 0.01
Memory access in virtual memory mapping for some microprocessors may allow an authenticated user to potentially enable information disclosure via local access.
- risk 0.21cvss 3.3epss 0.00
Logic condition in specific microprocessors may allow an authenticated user to potentially enable partial physical address information disclosure via local access.