Spectre Vulnerabilities Found in Commercial RISC-V Processors
Researchers have demonstrated that certain out-of-order RISC-V processors, including SiFive P550 and T-Head Xuantie variants, are susceptible to multiple Spectre attack variants, capable of leaking arbitrary kernel memory.
The Spectre family of vulnerabilities, notorious for exploiting speculative execution in modern processors, has resurfaced with researchers confirming its presence in certain commercial RISC-V chips. While often assumed to be immune due to the architecture's perceived simplicity, this assumption is now proven incorrect for out-of-order RISC-V designs.
Researchers from academic institutions in Belgium and Germany detailed their findings in a paper accepted at the 35th Usenix Security Symposium, titled "Spectre on RISC-V Silicon: Attacks and Defenses on Commercial Out-of-Order Processors." Their work specifically targets commercially available out-of-order RISC-V processors, namely the SiFive P550 and Alibaba's T-Head Xuantie C910/C920. In contrast, in-order RISC-V processors like the SiFive U74 and Xuantie C906/C908 appear to be unaffected.
Previous research had identified Spectre vulnerabilities in RISC-V processors used in academic settings, but this new study is the first to address commercial silicon. The researchers successfully demonstrated proof-of-concept attacks using several Spectre variants, including Spectre-PHT (Pattern History Table), Spectre-BTB (Branch Target Buffer), Spectre-RSB (Return Stack Buffer), and Spectre-STL (Store To Load). These attacks achieved high recall and precision rates, indicating a significant risk.
To illustrate the practical implications, the team developed a Spectre exploit capable of leaking arbitrary Linux kernel memory from the T-Head Xuantie C910 processor at a rate of 338 bytes per second. This capability highlights the potential for sensitive data exfiltration from affected systems.
While software-based mitigations for Spectre exist for x86 and ARM architectures, the researchers note that these defenses are not directly transferable to RISC-V. They also point out a critical lack of introspection interfaces in current RISC-V hardware, which hinders the ability to observe and manage microarchitectural features essential for effective defense. The diverse nature of the RISC-V hardware ecosystem further complicates the development of a universal mitigation strategy.
The authors conclude that RISC-V, while inheriting the software and threat models of mature architectures, lacks their accumulated hardening. Addressing these Spectre vulnerabilities requires more than just porting existing mitigations; it necessitates the development of new architectural primitives, enhanced hardware transparency, and robust ecosystem-wide tooling.
Responsible disclosure of these findings occurred in December. Three patches have since been merged into the mainline Linux kernel, with two more under review. SiFive has reportedly addressed findings specific to its P550 processor, and T-Head has committed to releasing speculation barriers for its processors. The researchers opted not to delay publication, given the long-standing nature of Spectre vulnerabilities.
The research team comprised Lukas Gerlach and Michael Schwarz from CISPA Helmholtz Center for Information Security, and Marton Bognar and Jo Van Bulck from DistriNet, KU Leuven. Their work underscores the ongoing challenges in securing modern processor architectures against well-established vulnerability classes.