New 'DRAM Scrambling' Attack Bypasses CPU Hardware Security
A novel attack technique dubbed 'DRAM Scrambling' can bypass critical hardware security boundaries in modern CPUs by manipulating memory controller address translation.
Security researcher Christopher Domas has unveiled a groundbreaking attack technique, termed 'DRAM Scrambling,' that targets the fundamental memory controller logic within modern CPUs. This method allows attackers to bypass some of the most robust hardware security measures, including protections for System Management Mode (SMM), the Platform Security Processor (PSP), and even CPU microcode.
The attack exploits the way physical memory addresses are translated into actual DRAM coordinates. Every memory access from a CPU core passes through the memory controller, which remaps these logical addresses into physical locations on the DRAM modules. Security features like AMD's SEV, Intel's SGX, and ARM's TrustZone all rely on the assumption that these physical address mappings remain fixed and predictable. DRAM Scrambling breaks this assumption by altering the memory controller's configuration bits, effectively 'spaghettifying' the memory mapping.
Once the memory mapping is altered, an attacker can make one physical address point to the same DRAM cell as another, previously inaccessible, address. Crucially, existing access control mechanisms operate at the physical address level and do not verify the underlying DRAM coordinates. This means they are unaware that the memory map has been manipulated, leaving protected regions vulnerable.
Unlike traditional software vulnerabilities, DRAM Scrambling is not easily patchable through a simple firmware update. The research highlights that the address translation performed by memory controllers is a linear operation that can be mathematically reconstructed. By using tools like SMT solvers, attackers can reverse-engineer the remapping process even when manufacturers do not fully document the controller's registers.
Domas demonstrated the attack on older AMD processors, successfully extracting sensitive data. This included the fTPM's RSA signing routine from the isolated Platform Security Processor, the System Management Mode interrupt handler from protected SMRAM, and even raw CPU register states stored in DRAM during low-power idle states. Perhaps most alarmingly, the attack can also read and overwrite CPU microcode patches that are temporarily written to DRAM during idle transitions.
While the initial proof-of-concept targeted a specific AMD architecture, the underlying principles of DRAM Scrambling are present across a wide range of modern CPU designs. The research indicates that similar memory controller patterns, including channel and rank interleaving, bank swizzling, and chip-select mapping, exist in processors from AMD, Intel, ARM, and RISC-V architectures.
The implications of this attack are significant, as it operates at a layer beneath most existing security defenses. Traditional CPU security models are ill-equipped to handle vulnerabilities that manipulate the very fabric of memory addressing. The findings, set to be presented at Black Hat 2026, are expected to prompt significant attention from chip manufacturers and the broader cybersecurity community regarding how to address this fundamental hardware security challenge.
This research underscores a growing trend of sophisticated hardware-level attacks that challenge the assumptions underlying modern computer security. As processors become more complex, new avenues for exploitation continue to emerge, requiring innovative defense strategies that extend beyond software patches.