Ryzen Pro 3900 Firmware
by AMD
CVEs (6)
| CVE | Vendor / Product | Sev | Risk | CVSS | EPSS | KEV | Published | Description |
|---|---|---|---|---|---|---|---|---|
| CVE-2023-20571 | Hig | 0.53 | 8.1 | 0.00 | Nov 14, 2023 | A race condition in System Management Mode (SMM) code may allow an attacker using a compromised user space to leverage CVE-2018-8897 potentially resulting in privilege escalation. | ||
| CVE-2023-20565 | Hig | 0.51 | 7.8 | 0.00 | Nov 14, 2023 | Insufficient protections in System Management Mode (SMM) code may allow an attacker to potentially enable escalation of privilege via local access. | ||
| CVE-2023-20563 | Hig | 0.51 | 7.8 | 0.00 | Nov 14, 2023 | Insufficient protections in System Management Mode (SMM) code may allow an attacker to potentially enable escalation of privilege via local access. | ||
| CVE-2020-12965 | Hig | 0.49 | 7.5 | 0.02 | Feb 4, 2022 | When combined with specific software sequences, AMD CPUs may transiently execute non-canonical loads and store using only the lower 48 address bits potentially resulting in data leakage. | ||
| CVE-2021-26346 | Med | 0.36 | 5.5 | 0.00 | Jan 11, 2023 | Failure to validate the integer operand in ASP (AMD Secure Processor) bootloader may allow an attacker to introduce an integer overflow in the L2 directory table in SPI flash resulting in a potential denial of service. | ||
| CVE-2021-26337 | Med | 0.36 | 5.5 | 0.00 | Nov 16, 2021 | Insufficient DRAM address validation in System Management Unit (SMU) may result in a DMA read from invalid DRAM address to SRAM resulting in SMU not servicing further requests. |
- risk 0.53cvss 8.1epss 0.00
A race condition in System Management Mode (SMM) code may allow an attacker using a compromised user space to leverage CVE-2018-8897 potentially resulting in privilege escalation.
- risk 0.51cvss 7.8epss 0.00
Insufficient protections in System Management Mode (SMM) code may allow an attacker to potentially enable escalation of privilege via local access.
- risk 0.51cvss 7.8epss 0.00
Insufficient protections in System Management Mode (SMM) code may allow an attacker to potentially enable escalation of privilege via local access.
- risk 0.49cvss 7.5epss 0.02
When combined with specific software sequences, AMD CPUs may transiently execute non-canonical loads and store using only the lower 48 address bits potentially resulting in data leakage.
- risk 0.36cvss 5.5epss 0.00
Failure to validate the integer operand in ASP (AMD Secure Processor) bootloader may allow an attacker to introduce an integer overflow in the L2 directory table in SPI flash resulting in a potential denial of service.
- risk 0.36cvss 5.5epss 0.00
Insufficient DRAM address validation in System Management Unit (SMU) may result in a DMA read from invalid DRAM address to SRAM resulting in SMU not servicing further requests.