rpm package
opensuse/xen&distro=openSUSE Leap Micro 5.5
pkg:rpm/opensuse/xen&distro=openSUSE%20Leap%20Micro%205.5
Vulnerabilities (7)
| CVE | Sev | CVSS | KEV | Affected versions | Fixed in | Published | Description |
|---|---|---|---|---|---|---|---|
| CVE-2024-45819 | — | < 4.17.5_06-150500.3.42.1 | 4.17.5_06-150500.3.42.1 | Dec 19, 2024 | PVH guests have their ACPI tables constructed by the toolstack. The construction involves building the tables in local memory, which are then copied into guest memory. While actually used parts of the local memory are filled in correctly, excess space that is being allocated is | ||
| CVE-2024-45818 | — | < 4.17.5_06-150500.3.42.1 | 4.17.5_06-150500.3.42.1 | Dec 19, 2024 | The hypervisor contains code to accelerate VGA memory accesses for HVM guests, when the (virtual) VGA is in "standard" mode. Locking involved there has an unusual discipline, leaving a lock acquired past the return from the function that acquired it. This behavior results in a | ||
| CVE-2024-45817 | — | < 4.17.5_04-150500.3.39.1 | 4.17.5_04-150500.3.39.1 | Sep 25, 2024 | In x86's APIC (Advanced Programmable Interrupt Controller) architecture, error conditions are reported in a status register. Furthermore, the OS can opt to receive an interrupt when a new error occurs. It is possible to configure the error interrupt with an illegal vector, whic | ||
| CVE-2024-31146 | — | < 4.17.5_02-150500.3.36.1 | 4.17.5_02-150500.3.36.1 | Sep 25, 2024 | When multiple devices share resources and one of them is to be passed through to a guest, security of the entire system and of respective guests individually cannot really be guaranteed without knowing internals of any of the involved guests. Therefore such a configuration canno | ||
| CVE-2024-31145 | — | < 4.17.5_02-150500.3.36.1 | 4.17.5_02-150500.3.36.1 | Sep 25, 2024 | Certain PCI devices in a system might be assigned Reserved Memory Regions (specified via Reserved Memory Region Reporting, "RMRR") for Intel VT-d or Unity Mapping ranges for AMD-Vi. These are typically used for platform tasks such as legacy USB emulation. Since the precise purp | ||
| CVE-2024-31143 | — | < 4.17.4_04-150500.3.33.1 | 4.17.4_04-150500.3.33.1 | Jul 18, 2024 | An optional feature of PCI MSI called "Multiple Message" allows a device to use multiple consecutive interrupt vectors. Unlike for MSI-X, the setting up of these consecutive vectors needs to happen all in one go. In this handling an error path could be taken in different situat | ||
| CVE-2023-46842 | — | < 4.17.4_04-150500.3.33.1 | 4.17.4_04-150500.3.33.1 | May 16, 2024 | Unlike 32-bit PV guests, HVM guests may switch freely between 64-bit and other modes. This in particular means that they may set registers used to pass 32-bit-mode hypercall arguments to values outside of the range 32-bit code would be able to set them to. When processing of hy |
- CVE-2024-45819Dec 19, 2024affected < 4.17.5_06-150500.3.42.1fixed 4.17.5_06-150500.3.42.1
PVH guests have their ACPI tables constructed by the toolstack. The construction involves building the tables in local memory, which are then copied into guest memory. While actually used parts of the local memory are filled in correctly, excess space that is being allocated is
- CVE-2024-45818Dec 19, 2024affected < 4.17.5_06-150500.3.42.1fixed 4.17.5_06-150500.3.42.1
The hypervisor contains code to accelerate VGA memory accesses for HVM guests, when the (virtual) VGA is in "standard" mode. Locking involved there has an unusual discipline, leaving a lock acquired past the return from the function that acquired it. This behavior results in a
- CVE-2024-45817Sep 25, 2024affected < 4.17.5_04-150500.3.39.1fixed 4.17.5_04-150500.3.39.1
In x86's APIC (Advanced Programmable Interrupt Controller) architecture, error conditions are reported in a status register. Furthermore, the OS can opt to receive an interrupt when a new error occurs. It is possible to configure the error interrupt with an illegal vector, whic
- CVE-2024-31146Sep 25, 2024affected < 4.17.5_02-150500.3.36.1fixed 4.17.5_02-150500.3.36.1
When multiple devices share resources and one of them is to be passed through to a guest, security of the entire system and of respective guests individually cannot really be guaranteed without knowing internals of any of the involved guests. Therefore such a configuration canno
- CVE-2024-31145Sep 25, 2024affected < 4.17.5_02-150500.3.36.1fixed 4.17.5_02-150500.3.36.1
Certain PCI devices in a system might be assigned Reserved Memory Regions (specified via Reserved Memory Region Reporting, "RMRR") for Intel VT-d or Unity Mapping ranges for AMD-Vi. These are typically used for platform tasks such as legacy USB emulation. Since the precise purp
- CVE-2024-31143Jul 18, 2024affected < 4.17.4_04-150500.3.33.1fixed 4.17.4_04-150500.3.33.1
An optional feature of PCI MSI called "Multiple Message" allows a device to use multiple consecutive interrupt vectors. Unlike for MSI-X, the setting up of these consecutive vectors needs to happen all in one go. In this handling an error path could be taken in different situat
- CVE-2023-46842May 16, 2024affected < 4.17.4_04-150500.3.33.1fixed 4.17.4_04-150500.3.33.1
Unlike 32-bit PV guests, HVM guests may switch freely between 64-bit and other modes. This in particular means that they may set registers used to pass 32-bit-mode hypercall arguments to values outside of the range 32-bit code would be able to set them to. When processing of hy