rpm package
opensuse/xen&distro=openSUSE Leap 15.6
pkg:rpm/opensuse/xen&distro=openSUSE%20Leap%2015.6
Vulnerabilities (23)
| CVE | Sev | CVSS | KEV | Affected versions | Fixed in | Published | Description |
|---|---|---|---|---|---|---|---|
| CVE-2026-23555 | Hig | 7.1 | < 4.18.5_12-150600.3.40.1 | 4.18.5_12-150600.3.40.1 | Mar 23, 2026 | Any guest issuing a Xenstore command accessing a node using the (illegal) node path "/local/domain/", will crash xenstored due to a clobbered error indicator in xenstored when verifying the node path. Note that the crash is forced via a failing assert() statement in xenstored. I | |
| CVE-2026-23554 | Hig | 7.8 | < 4.18.5_12-150600.3.40.1 | 4.18.5_12-150600.3.40.1 | Mar 23, 2026 | The Intel EPT paging code uses an optimization to defer flushing of any cached EPT state until the p2m lock is dropped, so that multiple modifications done under the same locked region only issue a single flush. Freeing of paging structures however is not deferred until the flus | |
| CVE-2026-23553 | — | < 4.18.5_10-150600.3.37.1 | 4.18.5_10-150600.3.37.1 | Jan 28, 2026 | In the context switch logic Xen attempts to skip an IBPB in the case of a vCPU returning to a CPU on which it was the previous vCPU to run. While safe for Xen's isolation between vCPUs, this prevents the guest kernel correctly isolating between tasks. Consider: 1) vCPU runs on | ||
| CVE-2025-58150 | — | < 4.18.5_10-150600.3.37.1 | 4.18.5_10-150600.3.37.1 | Jan 28, 2026 | Shadow mode tracing code uses a set of per-CPU variables to avoid cumbersome parameter passing. Some of these variables are written to with guest controlled data, of guest controllable size. That size can be larger than the variable, and bounding of the writes was missing. | ||
| CVE-2025-58149 | — | < 4.18.5_08-150600.3.34.2 | 4.18.5_08-150600.3.34.2 | Oct 31, 2025 | When passing through PCI devices, the detach logic in libxl won't remove access permissions to any 64bit memory BARs the device might have. As a result a domain can still have access any 64bit memory BAR when such device is no longer assigned to the domain. For PV domains the p | ||
| CVE-2025-58148 | — | < 4.18.5_06-150600.3.31.2 | 4.18.5_06-150600.3.31.2 | Oct 31, 2025 | [This CNA information record relates to multiple CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Some Viridian hypercalls can specify a mask of vCPU IDs as an input, in one of three formats. Xen has boundary checking bugs with all three formats, | ||
| CVE-2025-58147 | — | < 4.18.5_06-150600.3.31.2 | 4.18.5_06-150600.3.31.2 | Oct 31, 2025 | [This CNA information record relates to multiple CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Some Viridian hypercalls can specify a mask of vCPU IDs as an input, in one of three formats. Xen has boundary checking bugs with all three formats, | ||
| CVE-2025-58143 | — | < 4.18.5_06-150600.3.31.2 | 4.18.5_06-150600.3.31.2 | Sep 11, 2025 | [This CNA information record relates to multiple CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] There are multiple issues related to the handling and accessing of guest memory pages in the viridian code: 1. A NULL pointer dereference in the upd | ||
| CVE-2025-58142 | — | < 4.18.5_06-150600.3.31.2 | 4.18.5_06-150600.3.31.2 | Sep 11, 2025 | [This CNA information record relates to multiple CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] There are multiple issues related to the handling and accessing of guest memory pages in the viridian code: 1. A NULL pointer dereference in the upd | ||
| CVE-2025-27466 | — | < 4.18.5_06-150600.3.31.2 | 4.18.5_06-150600.3.31.2 | Sep 11, 2025 | [This CNA information record relates to multiple CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] There are multiple issues related to the handling and accessing of guest memory pages in the viridian code: 1. A NULL pointer dereference in the upd | ||
| CVE-2025-1713 | — | < 4.18.4_06-150600.3.20.1 | 4.18.4_06-150600.3.20.1 | Jul 17, 2025 | When setting up interrupt remapping for legacy PCI(-X) devices, including PCI(-X) bridges, a lookup of the upstream bridge is required. This lookup, itself involving acquiring of a lock, is done in a context where acquiring that lock is unsafe. This can lead to a deadlock. | ||
| CVE-2025-27465 | — | < 4.18.5_04-150600.3.28.1 | 4.18.5_04-150600.3.28.1 | Jul 16, 2025 | Certain instructions need intercepting and emulating by Xen. In some cases Xen emulates the instruction by replaying it, using an executable stub. Some instructions may raise an exception, which is supposed to be handled gracefully. Certain replayed instructions have additiona | ||
| CVE-2024-36357 | Med | 5.6 | < 4.18.5_04-150600.3.28.1 | 4.18.5_04-150600.3.28.1 | Jul 8, 2025 | A transient execution vulnerability in some AMD processors may allow an attacker to infer data in the L1D cache, potentially resulting in the leakage of sensitive information across privileged boundaries. | |
| CVE-2024-36350 | Med | 5.6 | < 4.18.5_04-150600.3.28.1 | 4.18.5_04-150600.3.28.1 | Jul 8, 2025 | A transient execution vulnerability in some AMD processors may allow an attacker to infer data from previous stores, potentially resulting in the leakage of privileged information. | |
| CVE-2024-28956 | Med | 5.6 | < 4.18.5_02-150600.3.23.1 | 4.18.5_02-150600.3.23.1 | May 13, 2025 | Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access. | |
| CVE-2024-53241 | — | < 4.18.4_02-150600.3.15.2 | 4.18.4_02-150600.3.15.2 | Dec 24, 2024 | In the Linux kernel, the following vulnerability has been resolved: x86/xen: don't do PV iret hypercall through hypercall page Instead of jumping to the Xen hypercall page for doing the iret hypercall, directly code the required sequence in xen-asm.S. This is done in preparati | ||
| CVE-2024-45819 | — | < 4.18.3_06-150600.3.12.1 | 4.18.3_06-150600.3.12.1 | Dec 19, 2024 | PVH guests have their ACPI tables constructed by the toolstack. The construction involves building the tables in local memory, which are then copied into guest memory. While actually used parts of the local memory are filled in correctly, excess space that is being allocated is | ||
| CVE-2024-45818 | — | < 4.18.3_06-150600.3.12.1 | 4.18.3_06-150600.3.12.1 | Dec 19, 2024 | The hypervisor contains code to accelerate VGA memory accesses for HVM guests, when the (virtual) VGA is in "standard" mode. Locking involved there has an unusual discipline, leaving a lock acquired past the return from the function that acquired it. This behavior results in a | ||
| CVE-2024-45817 | — | < 4.18.3_04-150600.3.9.1 | 4.18.3_04-150600.3.9.1 | Sep 25, 2024 | In x86's APIC (Advanced Programmable Interrupt Controller) architecture, error conditions are reported in a status register. Furthermore, the OS can opt to receive an interrupt when a new error occurs. It is possible to configure the error interrupt with an illegal vector, whic | ||
| CVE-2024-31146 | — | < 4.18.3_02-150600.3.6.1 | 4.18.3_02-150600.3.6.1 | Sep 25, 2024 | When multiple devices share resources and one of them is to be passed through to a guest, security of the entire system and of respective guests individually cannot really be guaranteed without knowing internals of any of the involved guests. Therefore such a configuration canno |
- affected < 4.18.5_12-150600.3.40.1fixed 4.18.5_12-150600.3.40.1
Any guest issuing a Xenstore command accessing a node using the (illegal) node path "/local/domain/", will crash xenstored due to a clobbered error indicator in xenstored when verifying the node path. Note that the crash is forced via a failing assert() statement in xenstored. I
- affected < 4.18.5_12-150600.3.40.1fixed 4.18.5_12-150600.3.40.1
The Intel EPT paging code uses an optimization to defer flushing of any cached EPT state until the p2m lock is dropped, so that multiple modifications done under the same locked region only issue a single flush. Freeing of paging structures however is not deferred until the flus
- CVE-2026-23553Jan 28, 2026affected < 4.18.5_10-150600.3.37.1fixed 4.18.5_10-150600.3.37.1
In the context switch logic Xen attempts to skip an IBPB in the case of a vCPU returning to a CPU on which it was the previous vCPU to run. While safe for Xen's isolation between vCPUs, this prevents the guest kernel correctly isolating between tasks. Consider: 1) vCPU runs on
- CVE-2025-58150Jan 28, 2026affected < 4.18.5_10-150600.3.37.1fixed 4.18.5_10-150600.3.37.1
Shadow mode tracing code uses a set of per-CPU variables to avoid cumbersome parameter passing. Some of these variables are written to with guest controlled data, of guest controllable size. That size can be larger than the variable, and bounding of the writes was missing.
- CVE-2025-58149Oct 31, 2025affected < 4.18.5_08-150600.3.34.2fixed 4.18.5_08-150600.3.34.2
When passing through PCI devices, the detach logic in libxl won't remove access permissions to any 64bit memory BARs the device might have. As a result a domain can still have access any 64bit memory BAR when such device is no longer assigned to the domain. For PV domains the p
- CVE-2025-58148Oct 31, 2025affected < 4.18.5_06-150600.3.31.2fixed 4.18.5_06-150600.3.31.2
[This CNA information record relates to multiple CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Some Viridian hypercalls can specify a mask of vCPU IDs as an input, in one of three formats. Xen has boundary checking bugs with all three formats,
- CVE-2025-58147Oct 31, 2025affected < 4.18.5_06-150600.3.31.2fixed 4.18.5_06-150600.3.31.2
[This CNA information record relates to multiple CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] Some Viridian hypercalls can specify a mask of vCPU IDs as an input, in one of three formats. Xen has boundary checking bugs with all three formats,
- CVE-2025-58143Sep 11, 2025affected < 4.18.5_06-150600.3.31.2fixed 4.18.5_06-150600.3.31.2
[This CNA information record relates to multiple CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] There are multiple issues related to the handling and accessing of guest memory pages in the viridian code: 1. A NULL pointer dereference in the upd
- CVE-2025-58142Sep 11, 2025affected < 4.18.5_06-150600.3.31.2fixed 4.18.5_06-150600.3.31.2
[This CNA information record relates to multiple CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] There are multiple issues related to the handling and accessing of guest memory pages in the viridian code: 1. A NULL pointer dereference in the upd
- CVE-2025-27466Sep 11, 2025affected < 4.18.5_06-150600.3.31.2fixed 4.18.5_06-150600.3.31.2
[This CNA information record relates to multiple CVEs; the text explains which aspects/vulnerabilities correspond to which CVE.] There are multiple issues related to the handling and accessing of guest memory pages in the viridian code: 1. A NULL pointer dereference in the upd
- CVE-2025-1713Jul 17, 2025affected < 4.18.4_06-150600.3.20.1fixed 4.18.4_06-150600.3.20.1
When setting up interrupt remapping for legacy PCI(-X) devices, including PCI(-X) bridges, a lookup of the upstream bridge is required. This lookup, itself involving acquiring of a lock, is done in a context where acquiring that lock is unsafe. This can lead to a deadlock.
- CVE-2025-27465Jul 16, 2025affected < 4.18.5_04-150600.3.28.1fixed 4.18.5_04-150600.3.28.1
Certain instructions need intercepting and emulating by Xen. In some cases Xen emulates the instruction by replaying it, using an executable stub. Some instructions may raise an exception, which is supposed to be handled gracefully. Certain replayed instructions have additiona
- affected < 4.18.5_04-150600.3.28.1fixed 4.18.5_04-150600.3.28.1
A transient execution vulnerability in some AMD processors may allow an attacker to infer data in the L1D cache, potentially resulting in the leakage of sensitive information across privileged boundaries.
- affected < 4.18.5_04-150600.3.28.1fixed 4.18.5_04-150600.3.28.1
A transient execution vulnerability in some AMD processors may allow an attacker to infer data from previous stores, potentially resulting in the leakage of privileged information.
- affected < 4.18.5_02-150600.3.23.1fixed 4.18.5_02-150600.3.23.1
Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.
- CVE-2024-53241Dec 24, 2024affected < 4.18.4_02-150600.3.15.2fixed 4.18.4_02-150600.3.15.2
In the Linux kernel, the following vulnerability has been resolved: x86/xen: don't do PV iret hypercall through hypercall page Instead of jumping to the Xen hypercall page for doing the iret hypercall, directly code the required sequence in xen-asm.S. This is done in preparati
- CVE-2024-45819Dec 19, 2024affected < 4.18.3_06-150600.3.12.1fixed 4.18.3_06-150600.3.12.1
PVH guests have their ACPI tables constructed by the toolstack. The construction involves building the tables in local memory, which are then copied into guest memory. While actually used parts of the local memory are filled in correctly, excess space that is being allocated is
- CVE-2024-45818Dec 19, 2024affected < 4.18.3_06-150600.3.12.1fixed 4.18.3_06-150600.3.12.1
The hypervisor contains code to accelerate VGA memory accesses for HVM guests, when the (virtual) VGA is in "standard" mode. Locking involved there has an unusual discipline, leaving a lock acquired past the return from the function that acquired it. This behavior results in a
- CVE-2024-45817Sep 25, 2024affected < 4.18.3_04-150600.3.9.1fixed 4.18.3_04-150600.3.9.1
In x86's APIC (Advanced Programmable Interrupt Controller) architecture, error conditions are reported in a status register. Furthermore, the OS can opt to receive an interrupt when a new error occurs. It is possible to configure the error interrupt with an illegal vector, whic
- CVE-2024-31146Sep 25, 2024affected < 4.18.3_02-150600.3.6.1fixed 4.18.3_02-150600.3.6.1
When multiple devices share resources and one of them is to be passed through to a guest, security of the entire system and of respective guests individually cannot really be guaranteed without knowing internals of any of the involved guests. Therefore such a configuration canno
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