CWE-1264
Hardware Logic with Insecure De-Synchronization between Control and Data Channels
BaseIncomplete
Description
The hardware logic for error handling and security checks can incorrectly forward data before the security check is complete.
Hierarchy (View 1000)
Parents
Children
none
Related attack patterns (CAPEC)
CAPEC-233 · CAPEC-663
CVEs mapped to this weakness (1)
| CVE | Sev | Risk | CVSS | EPSS | KEV | Published | Description |
|---|---|---|---|---|---|---|---|
| CVE-2024-21823 | Hig | 0.49 | 7.5 | 0.00 | May 16, 2024 | Hardware logic with insecure de-synchronization in Intel(R) DSA and Intel(R) IAA for some Intel(R) 4th or 5th generation Xeon(R) processors may allow an authorized user to potentially enable escalation of privilege local access |