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Medium severity6.5NVD Advisory· Published Nov 10, 2025· Updated Jun 17, 2026

CVE-2025-63384

CVE-2025-63384

Description

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.

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Affected products

3
  • Chipsalliance/Rocketchip2 versions
    cpe:2.3:a:chipsalliance:rocketchip:*:*:*:*:*:*:*:*+ 1 more
    • cpe:2.3:a:chipsalliance:rocketchip:*:*:*:*:*:*:*:*range: <=1.6
    • (no CPE)range: <=1.6
  • RISC-V/Rocket-Chipcpe-rescue

Patches

Vulnerability mechanics

News mentions

0

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