Critical severity9.1NVD Advisory· Published Jul 1, 2025· Updated Apr 15, 2026

CVE-2025-45006

Description

Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.

AI Insight

LLM-synthesized narrative grounded in this CVE's description and references.

Affected products

Heyfenny/Vulnerability Disclosurereferences

Patches

Vulnerability mechanics

References

github.com/heyfenny/Vulnerability_disclosure/blob/main/RISCV/Rocket-chip/CVE-2025-45006/details.mdnvd
lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specificationsnvd

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