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Unrated severityNVD Advisory· Published Jan 14, 2026· Updated Jan 20, 2026

CVE-2025-0647

CVE-2025-0647

Description

In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.

Affected products

11
  • Arm/C1-Premiumv5
    Range: 0
  • Arm/C1-Ultrav5
    Range: 0
  • Arm/Cortex-A710v5
    Range: 0
  • Arm/Cortex-X2v5
    Range: 0
  • Arm/Cortex-X3v5
    Range: 0
  • Arm/Cortex-X4v5
    Range: 0
  • Arm/Cortex-X925v5
    Range: 0
  • Arm/Neoverse-N2v5
    Range: 0
  • Arm/Neoverse-V2v5
    Range: 0
  • Arm/Neoverse-V3v5
    Range: 0
  • Arm/Neoverse-V3AEv5
    Range: 0

Patches

0

No patches discovered yet.

Vulnerability mechanics

AI mechanics synthesis has not run for this CVE yet.

References

1

News mentions

0

No linked articles in our index yet.