VYPR
Unrated severityNVD Advisory· Published Jan 5, 2024· Updated Nov 4, 2025

x86/AMD: missing IOMMU TLB flushing

CVE-2023-34326

Description

The caching invalidation guidelines from the AMD-Vi specification (48882—Rev 3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction (see stale DMA mappings) if some fields of the DTE are updated but the IOMMU TLB is not flushed.

Such stale DMA mappings can point to memory ranges not owned by the guest, thus allowing access to unindented memory regions.

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Affected products

31

Patches

Vulnerability mechanics

References

1

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